1. Field of the Invention
The present invention relates to a novel data processing system and more particularly to a virtually memory data processing system and the address conversion techniques for such a system.
2. Description of the Prior Art
A virtual memory system provides users with much a larger memory space than that of the main memory. A central processing unit (CPU) is provided with hardware called a dynamic address translator (DAT) for automatic translation of user's virtual memory space into the real memory space. The DAT includes an associative memory system as its major element.
FIG. 1 illustrates a prior art data processing system of this type. The data processing system includes the central processing unit CPU 11, an input/output channel (I/O channel) 10, and the main memory MM 14. A page table 15 is located in a portion of the main memory 14 for storing the relationship between the virtual address and the real address. This address relationship is often expressed by two tables, one of which is called a segment table and the other of which is called the page table. In the present invention, the two tables are together referred to as the page table.
The central processing unit CPU 11 includes a dynamic address translator DAT 12 to translate the virtual address into the real address by referring to the page table 15. Usually, the dynamic address translator DAT 12 includes the hardware of a so-called translation look-aside buffer TLB 13 for improving the speed of the address translation by storing the recently accessed portion of the page table 15 in the translation look-aside buffer TLB. These virtual addressing systems and their associated hardware are well known and thus will not be discussed in detail herein. Such systems are described in manuals, for example, "A guide to the IBM 4341 Processor Section 15" (GC20-1877) published by the IBM corporation.
In the prior art systems, the system architecture is designed aiming to minimize hardware costs and to improve the speed of the address conversion. However, recently there have been rapid improvements in semiconductor memory elements and thus it is easy and inexpensive to use such memory elements to form memories having large capacities and short memory access time. In view of these developments in hardware technology, such prior art conversion systems and their associated hardware are becoming obsolete.
In the prior art address conversion, the operating system OS can freely initialize and update the page table with general instructions, because the page table is stored in the main memory. However, as will be described below, the page table of the present invention is designed outside the main memory as will be described below. Thus, it is impossible to address the page table with the general instructions. In prior art technology as currently used, the operating system (OS) often adopts a static paging scheme rather than demand paging. In the static paging scheme, a group of pages relating to each other are processed as a whole in order to improve the efficiency of the system and also to shorten the system response time. It is important both for efficiency and response time purposes that the operating system can perform the static paging for a plurality of pages, even though there is no page table in the main memory, as disclosed in this specification.
A translation look-aside buffer (TLB) 13 of the prior art is shown in FIG. 2. In FIG. 2 the translation look-aside buffer TLB translates the virtual address space of a total of 16 MB megabytes divided into pages for unit of KB (kilobytes) and addressed by a virtual address of 24 bits into the real address of a maximum of 4 megabytes. The translation look-aside buffer TLB includes a set associative system, which is common in conventional translation look-aside buffers. The memories 21 and 24 store the upper bits of the virtual address accessed recently and the memories 22 and 25 store the upper bits of the real address corresponding to them.
For instance, assume that the memories have a capacity of 2.sup.N words. The portion of the virtual address, except the lower portion of 12 bits, is called a page number portion. The page number portion of the virtual address addresses the memories 21, 22, 24, and 25 with its lower N bits, and the comparators 23 and 26 compare the upper bits of the virtual address read from them with the remainder of the virtual address. The output of the comparators 23 and 26 are connected to the enable terminals of the memories 22 and 25, respectively. Thus, if the comparator 23 detects a coincidence, the real address corresponding to the associative address is read from the memory 22. Similarly if the comparator 26 detects a coincidence, the real address corresponding to the virtual address is read from the memory 25.